1. Field of the Invention
This invention pertains in general to a semiconductor device, and, more particularly, to a stack-film trench capacitor and method for manufacturing the same.
2. Description of the Prior Art
In the semiconductor industry, memory cells are among the most important integrated circuit devices and have been the source of continuing research. Continued developments have been undertaken in the industry to increase storage capacity, enhance charge retaining capability, improve writing and reading speed, and decrease device dimensions of memory cells. Many memory cells rely on capacitors as charge storage devices. For example, a dynamic random access memory (DRAM) cell generally includes a transistor and a capacitor controlled by the transistor. The capacitor is a single charge storage capacitor for storing a logical status. The transistor, which is commonly referred to as a pass transistor, controls the writing and reading of the logical status stored in the capacitor. The transistor may be a field-effect transistor (FET), and frequently, an N-channel field effect transistor (N-FET). To further illustrate the background of the related art without limiting the scope and application of the present invention, the following paragraphs describe the application of a capacitor in a DRAM.
Generally, a DRAM cell can be divided into three designs: planar, stacked-capacitor, and trench. In the planar design, the transistor and capacitor of a cell are produced as planar components. The planar design generally requires more area per memory cell than the other two designs because the capacitor and transistor occupy separate areas of a semiconductor substrate. In the stacked-capacitor design, the capacitor of a cell is disposed above the transistor to reduce the substrate area occupied by each cell. Various designs for vertically extending the capacitor have been developed in recent years. In the trench design, the transistor is disposed on the surface of a substrate, and the capacitor is disposed in a trench formed in the substrate. The trench design allows the formation of densely arranged memory cell arrays.
Generally, trench capacitors provide comparatively large capacitance while occupying a comparatively small area on a semiconductor chip surface. Trench capacitors are characterized by deep and narrow trenches formed in the semiconductor substrate. An insulator or dielectric formed on the trench walls serves as the capacitor dielectric. Generally, two capacitor electrodes are formed with the capacitor dielectric being disposed between the two electrodes. The capacitance (C) of a trench capacitor is determined as follows:C=∈A/d,
where ∈ is the permittivity of a capacitor dielectric, A is the surface area of the capacitor dielectric, which is disposed between the two electrodes, and d is the thickness of the capacitor dielectric, which is usually the distance between the two electrodes. From the foregoing relationship, the capacitance of a trench capacitor may be increased by providing a capacitor dielectric with a high permittivity (∈), forming a trench capacitor having a large surface area of a capacitor dielectric (A), or using a thin capacitor dielectric.
As the density of DRAM products increases, the space between trench capacitors decreases. Current deep trench technology has difficulties in providing satisfactory capacitance due to the strict space restrictions of modem devices. As an example, for DRAM devices of the 0.15 nm generation or beyond, especially for devices of the 0.9 nm generation or beyond, the traditional trench design has proven to be unsatisfactory in providing trench capacitors with sufficient capacitance.